The present invention relates to arithmetic and logic bit-shifting and bit-rotating architectures, and more particularly to a wide shift array structure that features low-voltage excursion sensing.
High-speed shift and rotation of bits within a field are required in a variety of arithmetic and logic applications for digital processors, e.g. core and auxiliary microprocessors embedded in computers and attached controllers. Floating-point units (FPUs) require particularly high-speed shift logic for normalization of operands within registers and along data paths. But simple (single-bit) or complex (plural-bit) shift and rotate instructions also may benefit from high-speed operation of shift logic. Numerous other applications such as digital signal processing (DSP), video imaging and enhancement, telecommunications and multimedia data manipulation, may benefit from high speed shift logic. In nearly all such applications, the width of the bit field to be shifted or rotated is increasing, with multi-word, i.e. thirty-two bit double-word and sixty-four bit quad-word, manipulations having already become commonplace.
Conventional shift logic requires multi-level multiplexing and buffering to accommodate wide bit fields, i.e. bit fields of more than four bits. This is primarily due to the speed requirements of the logic, which typically must produce shifted outputs at very high frequencies. It is also due to heavy current draws through parallel bit cells across the width of the shift logic versus the high voltage excursion output requirements of sensing circuits. It also is due at least in part to the relatively limited fan-in of complimentary metal oxide semiconductor (CMOS) gates that are used in their semiconductor implementation.
A sixty-four bit wide, two-dimensional rotational shift array have been proposed to operate at frequencies up to 1.0 Gigahertz (GHz). Such is reported in 1 GHz Logic Circuits with Sense Amplifiers, O. Takahashi, N. Aoki, J. Silberman and S. Dhong, 1998 Symposium on VLSI Circuits Digest of Technical Papers. The described rotational shift register (ROT) uses CMOS pass transistors, and a 1.8-volt VDD rail. ROT responsive to single-ended (not differential) inputs (A0-A63, R0-R63) produces single-ended outputs (B0-B63).
Another conventional approach to bit shifting and rotation is an array of connected single complementary transmission gates with pre-encoded shifting controls. Such a shift array typically uses either dynamic or static CMOS pass gates.
A recent development in shifting and rotation architectures is the dual-rail domino logic for use in floating point processors. With dual-rail domino designs, data are represented as differential signal pairs having complementary components. The dual-rail domino design features a multi-level shifter in which partial shift results are required to be routed to a next level of logic for further Boolean combination, with attendant propagation delay per level. Thus, the dual-rail domino design exhibits relatively high speed but the fact that it requires multiple levels of wide logic gates and routing of double signal pairs across each logic level and between successive logic levels creates a circuit density problem due to the wide routing channels that are required.
Data signal line and control signal line transitions induce voltage fluctuations in adjacent signal lines, a phenomenon called cross-talk. With cross-talk, data may be misinterpreted by the successive (downstream) logic circuitry. High-density layouts exacerbate the cross-talk problem because of the closer coupling between unrelated but physically proximate signals. Cross-talk occurs even when adjacent signals are routed on different layers within a circuit and even when signals are routed perpendicular to one another, although most common is cross-talk between signals that are routed in parallel on the same layer. High-voltage excursions on data signal lines also exacerbate the cross-talk problem. This is because the greater the voltage excursion, the greater the cross-talk inducement. Cross-talk creates a risk of misreading a datum, or shifted-in element, within a shift array structure.
The use of differential signal representation and small signal sensing can greatly improve the robustness of a circuit against the common mode noise introduced by cross-talk coupling and also can improve the speed-power product of the circuits.
Thus, there is a need for high-speed, low-power wide bit shift arrays compatible with the ever-increasing speed-power products that characterize current and future central processor units (CPUs), floating point processors (FPUs) and the like.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment, which proceeds with reference to the drawings.